Conventionally, various manufacturing methods for a plurality of semiconductor chips by dividing such a semiconductor wafer have been known. For example, a method for collectively forming semiconductor devices in a plurality of device-formation-regions provided on a wafer of single-crystal silicon or the like, mechanically cutting (i.e., by dicing) the wafer along dividing regions located between adjacent device-formation-regions and manufacturing semiconductor chips by individualizing the device-formation-regions is known.
Moreover, in such a wafer, an evaluation device, or a test device, that is called TEG, or a Test Element Group, is formed in the dividing regions. In various steps of the semiconductor chip manufacturing process, the actual device characteristics are monitored by investigating various characteristics by means of the thus-formed TEG.
Moreover, it is often the case where such a TEG is formed of a material that contains various kinds of metals and inorganic substances besides silicon and silicon oxide that are generally the principal materials of the wafer. Moreover, the formed TEG becomes unnecessary after the various characteristics are investigated, and the TEG is removed by cutting (dicing) in the stage of wafer dicing along the dividing regions.
Although shrinkage (narrowing) of the dividing regions has been promoted to increase the number of semiconductor chips obtainable per a wafer in recent years, there is a limitation in narrowing the width of the TEG formation region from the viewpoint of reliably carrying out various electrical measurements. Therefore, the dividing regions are narrowed by reducing a gap between the edge portion of the TEG formation region and the edge portion of the dividing regions.
On the other hand, chipping of generating minute fragments or microcrack of generating minute cracks are easily caused by impacts during cutting by a blade during wafer dicing, and therefore, it is necessary to carry out the cutting by the blade in a position located apart from the device-formation-region by some degree. Therefore, if the narrowing of the dividing regions as described above is promoted, it is a case where the TEG cannot completely be removed by the cutting. If the TEG partially remains unremoved a short circuit or the like occurs due to the contact of the TEG with the wiring pattern when the semiconductor chip is mounted, and there is concern that circuit failure might occur.
In order to suppress the occurrence of this problem, various methods have been considered as a method for removing the TEG by cutting, as disclosed in, for example, Japanese unexamined patent publications Nos. 2002-231659 and 2001-60568.
In recent years, plasma dicing using plasma etching has attracted attention as a novel dicing technology for wafer dividing (refer to, for example, Japanese unexamined patent publications Nos. 2004-172365 and 2003-197569). However, it is often the case that the TEG is formed of various metals and inorganic substances unlike silicon and silicon oxide. Accordingly, there is a problem that the TEG cannot completely be removed by the etching and remain unremoved by the plasma dicing (e.g., plasma dicing using a fluorine based plasma) that uses a gas for etching the silicon based material.
Therefore, removing the TEG by etching by performing the etching with the use gas type changed during the plasma dicing has been considered. However, a problem exists that time and labor for changing the gas type of the etching are needed in such a case, and the efficiency of the semiconductor chip manufacturing process is hindered.